| PART |
Description |
Maker |
| 74LV107 74LV107D 74LV107DB 74LV107N 74LV107PW 74LV |
CLP SINE LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74ACT112D MC74ACT112N MC74ACT112 ON1165 MC74AC11 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
From old datasheet system
|
Motorola Mobility Holdings, Inc.
Motorola, Inc
ON Semi
|
| SN54LS112A SN54LS112J 74LS112 SN74LS112N SN74LS112 |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
MOTOROLA[Motorola, Inc]
MOTOROLA[Motorola Inc]
|
| SN74LS112D |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
|
Motorola, Inc
|
| 74HC107D-Q100 74HCT107D-Q100 74HC107PW-Q100 |
Dual JK flip-flop with reset; negative-edge trigger
|
NXP Semiconductors
|
| IDT74LVC112A 74LVC112A_DS_87847 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
From old datasheet system
|
IDT
|
| 74F114PC |
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
|
Fairchild Semiconductor
|
| 74F113 I74F113D I74F113N N74F113D N74F113N 74F113_ |
From old datasheet system
Dual J-K negative edge-triggered flip-flops without reset
|
NXP Semiconductors
PHILIPS[Philips Semiconductors]
|
| IDT74LVC11 |
3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5V TOLERANT I/O
|
IDT
|
| CD74ACT112E |
ACT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
|
HARRIS SEMICONDUCTOR
|
| CD74HCT107E CD74HC107M96 CD74HC107MT |
<font color=red>[Old version datasheet]</font> Dual J-K Flip-Flop with Reset Negative-Edge Trigger
|
TI store
|
